Testing the delay of LPC804 PLU LUTs2018-04-18
The LPC804 is a new low-end microcontroller from NXP in the LPC8xx range. The LPC804 is interesting, because so far it is the only LPC microcontroller which contains a Programmable Logic Unit (PLU), a miniature FPGA with 26 5-input lookup tables and 4 bits of state. Unfortunately NXP doesn't publish the timing parameters of this circuitry. You are supposed to use NXPs proprietary PLU configuration tool, which is available only for Microsoft Windows.
The LUTs are chained together so that the output of LUT i is chosen as input 0 of LUT i+1, and each LUT puts input 0 through to its output (LUTnTRUTH is 0xaaaaaaaa). The input of LUT 0 is generated by the MCU via GPIO on a separate pin and fed into PLU input 2 on PIO0_10, which is muxed to input 0 of LUT 0.
The oscilloscope image show the input as trace 1 (yellow), trace 2 (green) is the output of LUT 0 (PLU output 2 on PIO0_16), and trace 3 (blue) is the output of LUT 10 (PLU output 6 on PIO0_13). The delay between traces 2 and 3 should be about 10 times the delay of a single LUT, including the connection from the output of the LUT to the input of the next LUT. So the delay is roughly 3.7ns per LUT, at room temperature.